FPGA Engineering Portfolio
Digital design • Signal processing • Hardware development
A structured journey from HDL fundamentals to satellite signal decoding.
Months 1–6 • Core HDL skills and communication protocols
Bidirectional serial communication with configurable baud rates, TX/RX FIFOs, and dual-language implementation (Verilog + VHDL).
Custom SPI master interfacing with accelerometer, gyroscope, and compass on the Blackboard. Integrates with UART for data output.
Months 7–12 • Memory systems, precision timing, VHDL proficiency
8-channel logic analyzer with SDRAM capture buffer, RLE compression, and sigrok/PulseView compatibility via SUMP protocol.
Precision timing reference disciplining a local oscillator to GPS time. Includes TDC, digital loop filter, and DAC control.
Months 13–18 • Software defined radio and real-time demodulation
Complete 1090 MHz ADS-B receiver with preamble detection, PPM demodulation, CRC validation, and dump1090-compatible output.
Months 19–24 • Complete satellite ground station
Complete satellite ground station receiving weather images from polar-orbiting satellites. QPSK demodulation with Costas loop, Viterbi decoding, Reed-Solomon FEC, and LRPT protocol.