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ADS-B Aircraft Decoder

Complete 1090 MHz receiver with real-time demodulation and message parsing.

Status
Not Started
Phase
Phase 3: Advanced (Months 15–16)
Platform
RealDigital Blackboard (Zynq-7000) + RTL-SDR

Overview

Build a complete ADS-B receiver demonstrating real-time signal processing and protocol implementation. ADS-B (Automatic Dependent Surveillance - Broadcast) is transmitted at 1090 MHz using Pulse Position Modulation (PPM).

Aircraft broadcast 112-bit messages containing identification, position, altitude, and velocity. The relatively simple modulation scheme makes this an excellent stepping stone toward the more complex satellite protocols in Phase 4.

This project directly demonstrates avionics domain knowledge relevant to NZ employers like Rocket Lab and aerospace startups.

System Architecture

RTL-SDR (1090 MHz) → USB → Zynq ARM → DMA/SPI → FPGA fabric → Decoded messages → Display

FPGA Requirements

  • Preamble detection (8 μs pattern matcher)
  • PPM demodulation and bit extraction
  • CRC-24 validation
  • Message type classification
  • FIFO for decoded messages

ARM Software Requirements

  • RTL-SDR USB interface and configuration
  • Sample streaming to FPGA via DMA
  • Message parsing and display
  • Optional: TCP server for dump1090 compatibility

Skills Demonstrated

  • Real-time Demodulation: PPM signal processing in hardware
  • Protocol Implementation: Working from ICAO specifications
  • CRC Algorithms: Hardware CRC-24 computation
  • System Integration: Complete RF-to-display pipeline
  • Avionics Domain: Mode S and ADS-B knowledge

Hardware Requirements

  • RTL-SDR V3 or V4 dongle (~$35–50 NZD)
  • 1090 MHz antenna (DIY or commercial)

Study Resources

  • The 1090 Megahertz Riddle by Junzi Sun (free online)
  • ICAO Doc 9871 – Mode S technical provisions
  • bladeRF ADS-B decoder source code (GitHub)

Prerequisites

This project requires understanding of:

  • I/Q sampling and complex baseband representation
  • Digital downconversion (DDC)
  • Modulation schemes (ASK, FSK, PSK)
  • RTL-SDR architecture and data interface

Architecture

Architecture will be documented as the project progresses.

Implementation Notes

Implementation notes will be added during development.

Resource Utilization

To be measured after implementation.

Progress Log

Not yet started

This project begins Phase 3 after SDR fundamentals study (Months 13–14).